Researchers at the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS) have fabricated functional gate‑all‑around transistors employing a stacked‑nanosheet architecture. The demonstration relied on immersion deep‑ultraviolet (DUV) lithography rather than extreme‑ultraviolet (EUV) tools, a technique the institute says could enable Chinese foundries to pursue 3nm‑class and smaller nodes without EUV equipment. The work was described in a report by DigiTimes.

The experimental flow presented by IMECAS is not yet a full production process for commercial chips; it serves only as a proof‑of‑concept for device structures. Critical dimensions and performance metrics that would allow direct comparison with established 3nm‑class offerings from other manufacturers have not been disclosed. Consequently, the institute has not announced a complete manufacturing flow for research‑grade chips, let alone a finished 3nm node.

While the achievement shows progress in alternative lithography methods, significant technical hurdles remain before such transistors can be integrated into mass‑produced silicon at the claimed process nodes.