China's CXMT plans to launch a DDR5 RDIMM product based on its 4F² memory cell architecture before the end of 2026, according to company president Dr. Cao Kanyu, who outlined the timeline during a speech at the 4th Integrated Chip and Chiplet Conference in Shanghai. The move positions CXMT approximately two years ahead of Samsung, which has indicated it will introduce 4F²-based memory products only in 2028. The 4F² architecture represents a shift from traditional planar designs to a stacked layout where each memory cell — composed of one transistor and one capacitor — is arranged vertically, reducing the cell footprint to a square measuring 4 times the minimum feature size squared. This design uses two bitlines and two wordlines per cell and enables up to a 50 percent increase in cell density per integrated circuit. CXMT began mass production of its G5 DRAM node, which employs SAQP (self-aligned quadruple patterning), and is preparing for a transition to G6 before advancing to monolithic 3D DRAM. The company is applying High-k Metal Gate (HKMG) technology using hafnium oxide to improve power efficiency and speed, particularly in its G4 process and LPDDR5X products. CXMT currently operates three 300mm DRAM fabs, each producing around 100,000 wafers per month, with plans to expand capacity to 600,000 wafers monthly by completing two new fabs in Shanghai and Hefei. The company also aims to increase HBM-focused output to 50,000 wafers per month by the end of 2026. Industry analysts note that CXMT is on track to surpass Micron in total volume production by 2030. Meanwhile, Samsung intends to implement 4F² using its B1b process — rebranded as D0a — with hybrid bonding separating memory cells from peripheral circuitry across different wafers before stacking them. This approach, while enabling advanced integration, is expected to maintain high pricing due to the cost of hybrid bonding.