Project Oberon System Version Runs on RISC-V Instead of RISC-5

A version of the Project Oberon System has been ported to run on RISC-V RV32 hardware using the OP2 compiler.

Project Oberon was created by Niklaus Wirth and Jürg Gutknecht at ETH Zürich between 1986 and 1989, resulting in an operating system, compiler, language, and development tools documented in the 1992 book Project Oberon. The 2013 revision of the project retains the goal of providing a complete, well‑documented system that can be used and studied. Originally the system ran on the National Semiconductor NS32032 processor, which is no longer available. Wirth designed a custom RISC‑5 processor and implemented it on an FPGA development board.

The repository contains the original Oberon‑07 source code, compiled to Oberon 90 for the OP2 compiler. The source archives were downloaded from projectoberon.net on 2026‑04‑14, including inner.zip, outer.zip, systools.zip, graph.zip, and apptools.zip. The code was modified to rename INTEGER to LONGINT, replace SYS.Mod built‑ins, and adjust type handling for byte‑sized data and string literals. A RISC‑V machine based on the rv32emu emulator was implemented, matching Wirth’s original memory map so that Kernel.Mod, Display.Mod, and Input.Mod remain unchanged. All modules are linked into a boot image that executes at startup without dynamic loading. Build scripts in the vm and root directories support compiling, linking, and running the system on Linux x64 and Windows x86. The rv32vm executable is platform specific; other files can be reused for building the VM on other platforms. Future work will target the Olimex ESP32‑P4‑PC board.

The migration demonstrates that the Oberon System can be moved to modern, inexpensive microcontrollers while preserving the original design principles. Ongoing development will focus on running the system natively on the ESP32‑P4‑PC hardware.