Dmitry Grinberg’s article “RISC‑V: They Should Have Known Better” appeared on Hacker News and sparked discussion on Lobsters. Grinberg argues that the RISC‑V instruction set is mismatched to cheap microcontroller applications because of features such as compressed store offsets and separate Zicsr extensions. He notes that developers in low‑resource regions often face high shipping costs and customs delays when obtaining development hardware, which he says influences the relevance of the architecture’s design. Grinberg contends that a high‑end CPU and a low‑cost microcontroller have opposing requirements, leading him to conclude that a single ISA cannot serve both markets effectively. Armstrong Subero, an embedded systems engineer from Trinidad and Tobago, responded with a detailed rebuttal that cites several commercially available RISC‑V devices. He points to the CH32V003, a ten‑cent RV32EC MCU with 16 registers, 2 KB SRAM and 16 KB flash, which he has used in a bin monitor and an agricultural door controller. He also describes the CH32H417, a dual‑core MCU with 896 KB SRAM, 960 KB flash, USB 3.2 Gen1 and Ethernet support, which runs a web browser and facial‑recognition algorithms with under 150 KB RAM. Subero highlights the Baochip open‑source VexRISC‑V core that includes an MMU and runs seL4 and Linux, as well as an ESP32‑C3 based RISC‑V chip used for an NES emulator. He notes that the OrangePi RV2 single‑board computer, initially $30 with free shipping, runs Linux and demonstrates the same instruction set across diverse form factors. He argues that the same ISA can be implemented with minimal registers and without a multiplier or divider in low‑cost chips, and that open licensing eliminates royalty fees, making RISC‑V viable for inexpensive embedded projects. Subero concludes that RISC‑V’s growth in the cheap microcontroller segment is driven by price, availability and an open ecosystem rather than ISA elegance, and that the debate over its suitability continues.