Cadence announced that its AI-driven digital and custom reference flows, tools, and solutions are certified for Intel’s 18A-P and 14A semiconductor process nodes, providing a signoff-ready pathway for AI, high‑performance computing and mobile system‑on‑chip designs. The certification builds on Intel Foundry’s latest process design kits and a multi‑year design technology co‑optimization agreement, as well as Cadence’s expanded design IP for the 18A and 18A‑P nodes. Cadence worked with Intel Foundry to co‑optimize its EDA tools, flows, and methodologies so they fully leverage features such as RibbonFET gate‑all‑around transistors and PowerVia/ PowerDirect backside power delivery technologies. The certified flows cover synthesis, place‑and‑route, timing and power signoff, physical verification, reliability verification, and analog/custom design, and are tuned to the Intel 18A‑P and 14A PDKs. Cadence also co‑developed an advanced packaging reference flow that supports Intel’s Embedded Multi‑die Interconnect Bridge (EMIB) and EMIB‑T, enabling concurrent design of multi‑chiplet architectures and early thermal, signal‑integrity and power‑integrity analysis. Silicon validation of Cadence IP and interface/memory IP on Intel 18A demonstrated interoperability. Intel 14A is expected to deliver higher performance at the same power relative to 18A, making it attractive for AI accelerators, cloud and edge HPC, premium mobile and future aerospace and government applications. Cadence’s Shawn Han and Boyd Phelps said the collaboration helps customers achieve power, performance and time‑to‑market goals. The company will showcase the certified flows and packaging solutions at the Design Automation Conference (DAC). Customers interested in early engagement on Intel 14A and advanced packaging projects are encouraged to contact Cadence and Intel Foundry representatives.