NVIDIA said its Vera CPUs can accelerate chip verification at Cadence and Synopsys by up to 1.5 times. Chip design requires three main EDA steps: simulation, verification, and implementation, before a die is sent to manufacturing. Verification is heavily dependent on CPU performance, prompting demand for faster cores and efficient memory. NVIDIA’s CUDA‑X libraries and cuLitho software have already reduced lithography costs and sped up design workflows. In initial tests, Vera CPUs achieved up to 1.5x faster execution in verification runs. Both Cadence Jasper and Synopsys VCS used an identical core count to measure the improvement. Faster verification reduces the time required for each run, increasing overall throughput. Engineers can therefore evaluate more design alternatives and complete additional validation within the same development period. NVIDIA’s Agent Toolkit includes PhysicsNeMo for AI‑driven physics modeling, cuISS for accelerating large sparse linear systems, cuDSS for high‑performance sparse solver support, and cuEST for quantum chemistry simulations that support density functional theory. These libraries are designed for integration into EDA and RTL coding workflows. The upcoming Rosa CPUs, based on the Rigel core architecture, are intended to further optimize EDA applications and support future NVIDIA CPUs and GPUs. The performance gains aim to shorten design cycles and lower development costs for semiconductor manufacturers.