TSMC's vice president of advanced packaging technology and services, Ho Chun, reported a 98% yield for CoWoS AI chip packages that use a 5.5x reticle size. The yield applies to several AI-related products assembled through the CoWoS process. CoWoS packaging combines multiple compute and memory chips into a larger final package, typically exceeding the size of an individual chip. The increased package area raises the likelihood of defects such as air bubbles in the underfill and bump misalignment. Ho said the company aims to extend the technology to a 14x reticle size by 2029. Scaling beyond three times the photomask size presents challenges, including heat tolerance and compliance with automotive-level mechanical and thermal requirements. Components must meet these standards during development to ensure reliable performance after packaging. The planned expansion is scheduled for 2029.