Fujitsu announced its Monaka CPU, a 3D‑stacked chip that combines a 2 nm, 144‑core processor with a 5 nm SRAM die, targeting a 2027 market introduction. The chip builds on the Arm v9.3‑A architecture and uses separate die for the CPU core, SRAM and I/O, a design intended for AI and high‑performance computing workloads. It will be offered in high‑performance and high‑efficiency variants with different clock speeds, TDPs and cooling requirements, and Fujitsu is beginning sampling now with volume production slated for 2027. The core die uses TSMC’s N2P process, while the SRAM and I/O die use N5, yielding about a 30 % reduction in silicon area compared with a monolithic 2 nm design. Each core occupies roughly 1.47 mm², and the architecture includes SVE2 vector support, FP8 and INT8MM data types, hybrid bonding between dies to reduce latency, per‑core DVFS, and RAS features such as ECC. The high‑performance SKU delivers a 2.9 GHz base clock, 500 W TDP, 6013 GFLOPS (DGEMM) and 96.2 TOPS (INT8), while the efficiency SKU runs at 2.1 GHz with a 350 W TDP, 4355 GFLOPS and 69.7 TOPS. Both variants support 96 PCIe 6.0/CXL 3.0 lanes, 12‑channel DDR5‑8000+ memory, and will be available with liquid or air cooling. Fujitsu plans to launch the Monaka‑X variant in 2029, which will incorporate NVIDIA NVLink Fusion and target the FugakuNext supercomputer. The company expects the Monaka family to lower total cost of ownership through ultra‑low‑voltage operation and to provide secure in‑use data protection via confidential computing, though specific market availability and pricing have not yet been disclosed.