NVIDIA announced a custom high‑bandwidth memory solution called NVHBM, developed with Amazon's Annapurna Labs, for use in future GPUs. Memory bandwidth has become increasingly important as AI models exceed trillion‑parameter scales. NVHBM places the memory controller inside the HBM base die rather than on the XPU, which NVIDIA says can increase bandwidth by up to 30% and reduce power consumption by 15% compared with the JEDEC HBM4E standard. The design also reduces main‑chip die area by up to 25% and cuts PHY and support area by as much as 67%. A narrower interface simplifies interposer routing, providing up to 80% more usable silicon across the layout. NVIDIA says these advantages translate into higher memory bandwidth, additional compute die area, and lower HBM power usage for AI accelerator programs. The company plans to establish a standard NVHBM implementation that will be supplied by multiple memory providers, aiming to reduce integration effort for customers. Participants in the NVLink Fusion ecosystem can bring AI chips to market more quickly. Annapurna Labs, an early partner, will integrate NVHBM with its NVLink scale‑up architecture for AWS Trainium4 chips, which will connect NVIDIA GPUs with Amazon silicon in a rack‑scale design. NVIDIA expects the first GPUs to adopt NVHBM when it launches in 2028.