D-Matrix announced its Raptor 3D DRAM, delivering 100 terabytes per second of bandwidth at 0.37 picojoules per bit with 32 gigabytes of capacity.
The solution stacks a TSMC 4 nm logic die on top of custom DRAM using 36 µm face‑to‑face bonding.
AI workloads require higher memory bandwidth and capacity as model sizes increase.
SRAM offers high speed but limited capacity and high cost, while HBM provides capacity but faces scaling challenges.
Raptor achieves 100 TB/s and 0.37 pJ/bit energy efficiency, supporting a junction temperature of 105 °C with refresh intervals of 4 ms.
Each chiplet contains 256 tensor engines and matches bank pitch to the tensor engines to reduce data movement.
The design avoids a physical layer and beachfront limit. It provides bandwidth and power characteristics similar to SRAM with higher capacity and lower power than HBM4, which delivers about 18 TB/s at 2–3 pJ/bit.
Compared with NVIDIA’s HBM4 in the Rubin R200 platform, Raptor shows 23.4 × higher bandwidth and 13.5 × better power efficiency.
Integration challenges include thermal management for DRAM‑on‑top stacks, power delivery via through‑silicon vias for logic‑on‑top stacks, and yield improvements through spare banks and error‑correcting codes.
The timing of other DRAM manufacturers’ 3D DRAM offerings remains uncertain.

